This application claims priority from Korean Patent Application No. 2002-59831, filed on Oct. 1, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a frequency multiplier and a method of multiplying the frequency of an external clock signal, a data output buffer, and a semiconductor device including the frequency multiplier and the data output buffer.
2. Description of the Related Art
In a process of designing a semiconductor device, a memory chip is tested to determine whether any of its memory cells have defects, following its fabrication. Memory chip tests can be performed during the semiconductor manufacturing process and/or after the memory chip is manufactured to check for normal operation.
In the test that is performed following manufacture of the memory chip, data is input to the semiconductor device, output from an output terminal of the semiconductor device, and tested.
The tests are performed by using test equipment for testing the semiconductor device. The test equipment inputs an external clock signal to the semiconductor device and receives an output signal with respect to data written in a memory cell from the semiconductor device. The output signal received from the semiconductor device by the test equipment is thus used to determine whether the memory cell has any defects.
In order to perform the tests, the clock signal frequencies of the semiconductor device and the test equipment have to be same as each other so that the test equipment can detect data output from the semiconductor device without any errors. However, the operating speeds of the semiconductor device and the test equipment are often times different from each other.
In particular, as the operating speed of the semiconductor devices becomes higher, the operation speed of the test equipment cannot keep up with the operating speed of the semiconductor device. Thus, the test is performed at the operating speed of the test equipment.
For example, when the operating speed of the semiconductor device is 400 MHz, while the operating speed of the test equipment is 100 MHz, the test is performed at the operating speed of the test equipment, i.e., 100 MHz. Since the operating speed of the test equipment is constant and can be changed only after the test equipment itself is changed, the test has to be performed at the operating speed of the test equipment.
For a semiconductor device which operates at low speed, a limited test equipment operating speed is tolerable. However, as the operating speed and the memory capacity of the semiconductor device increase, the operating speeds of the semiconductor device and the test equipment are not the same as each other. Thus, the time required for the test increases, and the test therefore becomes inefficient.
Since the time necessary for the test is directly related to the manufacturing cost of the semiconductor device, an increase in the time necessary for the test causes an increase in the manufacturing cost of the semiconductor device, which causes the cost of the semiconductor device to increase.
Therefore, a semiconductor device, which can be tested by test equipment at a low operating speed and can operate at a high speed, is required.